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Tomaitheous
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Joined: 27 Sep 2005
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Location: Tucson
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 Posted: Tue Oct 03, 2006 2:56 am Post subject: VDC DMA questions |
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Assuming 5mhz dot clock mode - How many clock cycles relative to the CPU speed does the VDC DMA take per word transfered? I figure it's probably faster than 6 CPU cycles per word.
Dave, I remember you saying that the DMA can happen while the VDC is reading from VRAM when it's in active display mode - correct? What happens when the DMA word read or write happens to be in the same location as the VDC is fetching for display? Also, the VDC reads a single BAT index word as a time instead of all the BAT indexes for the current line - correct?
Thanks,
Rich
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Tomaitheous
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| Posted: Sun Oct 08, 2006 8:42 pm Post subject: |
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Ok, according to Charles doc VRAM to VRAM DMA is halted during active display. I assume is resumes again during non-active display. So DMA read/write conflict with the VDC reads during active display are not an issue.
Based on this:
| Code: | During the active display period of a scanline, the VDC can do one 16-bit
access to VRAM on each cycle of the dot clock. Bits 1-0 of MWR tell the VDC
how to divide this amongst several sources:
1. CPU (reading or writing a word via register $02)
2. Background character pattern generator data (one read is for bitplanes
0 and 1, another is for bitplanes 2 and 3, either one or two are needed
per character)
3. BAT data (character name and palette, one fetch needed per character)
Bit Dot Dot cycles within an 8-dot unit
1 0 Width 0 1 2 3 4 5 6 7
-------------------------------------------
0 0 1 CPU BAT CPU ??? CPU CG0 CPU CG1
0 1 2 --BAT-- --CPU-- --CG0-- --CG1--
1 0 2 --BAT-- --CPU-- --CG0-- --CG0--
1 1 4 ------BAT------ ----CG0/CG1----
CPU - A read or write to register $02
BAT - The palette block and character name from the BAT
??? - Unknown, possibly an unused 'dummy' access
CG0 - Bitplanes 0, 1 from the character generator
CG1 - Bitplanes 2, 3 from the character generator
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Since the VDC can access 1 word per dot cycle it would be reasonable to say that worst case scenario would be 2-3 dot cycles per word transfer and 1 dot cycle per word in best case.
In 5.37mhz mode:
63.5us / 341 dot clocks = 186ns per clock cycle (or 1/5.37mhz). In comparison the CPU runs at 140ns per clock cycle - maybe this is were the 1 extra clock cycle comes in when writing to the VDC and VCE ports since it's faster than the slowest resolution mode. I wonder if the extra cycle is absent for 7.16mhz and 10.5mhz modes.
I'm not sure how many dot cycles the VRAM-VRAM DMA takes to setup.
One thing of interest is: assuming the VDC DMA's speed is based on the dot clock, one could speed up VRAM-VRAM DMA or SATB DMA by setting the VCE to 7.16mhz or 10.5mhz mode during or right before "BURST" mode.
I need to do some tests. If anyone has any additional info or corrections, please post 
Edit:
Ok, looks like the VRAM-VRAM DMA is only active during "Burst" mode just like the SATB DMA and not at the non-active parts of the scanline like I thought.
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Tomaitheous
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| Posted: Thu Oct 19, 2006 2:32 am Post subject: |
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Update:
I did some VRAM write tests during active display and it looks like the bandwidth is halved during this period. Looking at the dot period chart above, it appears the VDC delays the CPU if the CPU trys to write during a non-CPU access slot - in a string of continues writes to the VDC.
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Tomaitheous
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| Posted: Mon Oct 23, 2006 12:41 am Post subject: |
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Update 2:
I did timed ST1/ST2 during active display and with BG/SPR disabled - the speed for both were the same. So VRAM access during active display is not halved or reduced, but something is not adding up. The VDC must be fetching more than one BAT entry per 8 DOT period because if I try to race the VDC and change the BAT index for that current scanline a head of the VDC, the VDC eventually catches up about half way/middle of the screen.
Maybe "???" in the chart above is an additional BAT read to an internal BAT buffer.
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damage_x
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Joined: 20 Feb 2012
Posts: 4
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| Posted: Mon Feb 20, 2012 1:30 am Post subject: |
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| Tomaitheous wrote: | | Maybe "???" in the chart above is an additional BAT read to an internal BAT buffer. |
What about memory access for sprite graphics? If VDC can display 8 32-pixel-wide sprites per line in 256 resolution (does the limit change in higher resolutions?) then there should be as many sprite graphic fetches as for the BG character graphics. |
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